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vasyl_interrupts_and_vasyl_cpu_coordination [2020/10/07 13:25] – laubzegavasyl_interrupts_and_vasyl_cpu_coordination [2021/04/15 12:04] (current) – [VASYL interrupts and VASYL/CPU coordination] laubzega
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 === Non-VIC writes === === Non-VIC writes ===
  
-**MOV** and **XFER** display list instructions do an excellent job of fast, precise writes to VIC-II registers. However, there are locations in C64 memory space that influence video output, and yet are beyond VASYL's reach - a canonical example here is VIC bank switching in ''CI2PRA'' register at $dd00, but it could also be just-in-time Colour RAM or video matrix updates.+**MOV** and **XFER** display list instructions do an excellent job of fast, precise writes to VIC-II registers. However, there are locations in C64 memory space that influence video output, and yet are beyond VASYL's reach - a canonical example here is VIC bank switching in ''CI2PRA'' register at ''$dd00'', but it could also be just-in-time Color RAM or video matrix updates.
  
  
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         STA $315         STA $315
 </code> </code>
-  * The interrupt needs to be enabled by setting bit 4 in the ''IRQMASK'' register at $d01a (the same register that stores bits controlling VIC's interrupts),+  * The interrupt needs to be enabled by setting bit 4 in the ''IRQMASK'' register at ''$d01a'' (the same register that stores bits controlling VIC's interrupts),
  
 <code [enable_line_numbers="false"]> <code [enable_line_numbers="false"]>
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         IRQ         ; trigger another interrupt, this time at the beginning of the line         IRQ         ; trigger another interrupt, this time at the beginning of the line
 </code> </code>
-  * In your interrupt handler, you need to make sure that VASYL IRQ is acknowledged by setting bit 4 of ''VICIRQ'' register at $d019, or the interrupt will be retriggered as soon as the handler finishes executing.+  * In your interrupt handler, you need to make sure that VASYL IRQ is acknowledged by setting bit 4 of ''VICIRQ'' register at ''$d019'', or the interrupt will be retriggered as soon as the handler finishes executing.
  
 <code [enable_line_numbers="false"]> <code [enable_line_numbers="false"]>
vasyl_interrupts_and_vasyl_cpu_coordination.1602102318.txt.gz · Last modified: 2020/10/07 13:25 by laubzega