vasyl_interrupts_and_vasyl_cpu_coordination
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vasyl_interrupts_and_vasyl_cpu_coordination [2020/10/07 02:39] – silverdr | vasyl_interrupts_and_vasyl_cpu_coordination [2021/04/15 12:04] (current) – [VASYL interrupts and VASYL/CPU coordination] laubzega | ||
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While BeamRacer makes it easy to offload many graphics-related operations to VASYL, there are situations where some precisely-timed assistance from the main CPU may be needed. These can be chiefly grouped into three categories: | While BeamRacer makes it easy to offload many graphics-related operations to VASYL, there are situations where some precisely-timed assistance from the main CPU may be needed. These can be chiefly grouped into three categories: | ||
- | * Write to an address inaccessible to VASYL. | + | * Writing |
* Performing computations that 6510 is better suited to. | * Performing computations that 6510 is better suited to. | ||
* Making sure that CPU operations happen in a specific region of the video frame, to avoid clashes over resources shared with VASYL. | * Making sure that CPU operations happen in a specific region of the video frame, to avoid clashes over resources shared with VASYL. | ||
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=== Non-VIC writes === | === Non-VIC writes === | ||
- | **MOV** and **XFER** display list instructions do an excellent job of fast, precise writes to VIC-II registers. However, there are locations in C64 memory space that influence video output, and yet are beyond VASYL' | + | **MOV** and **XFER** display list instructions do an excellent job of fast, precise writes to VIC-II registers. However, there are locations in C64 memory space that influence video output, and yet are beyond VASYL' |
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Getting VASYL interrupts working is as easy (or as difficult), as setting up VIC raster interrupt: | Getting VASYL interrupts working is as easy (or as difficult), as setting up VIC raster interrupt: | ||
- | * They are delivered as IRQs, so depending on whether you want to rely on ROM interrupt handler or do the whole thing yourself, IRQ interrupt vector at either '' | + | * They are delivered as IRQs, so depending on your ROM configuration and whether you want to rely on the original |
<code [enable_line_numbers=" | <code [enable_line_numbers=" | ||
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STA $315 | STA $315 | ||
</ | </ | ||
- | * The interrupt needs to be enabled by setting bit 4 in the IRQMASK register at $d01a (the same register that stores bits controlling VIC's interrupts), | + | * The interrupt needs to be enabled by setting bit 4 in the '' |
<code [enable_line_numbers=" | <code [enable_line_numbers=" | ||
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IRQ ; trigger another interrupt, this time at the beginning of the line | IRQ ; trigger another interrupt, this time at the beginning of the line | ||
</ | </ | ||
- | * In your interrupt handler, you need to make sure that VASYL IRQ is acknowledged by setting bit 4 of register '' | + | * In your interrupt handler, you need to make sure that VASYL IRQ is acknowledged by setting bit 4 of '' |
<code [enable_line_numbers=" | <code [enable_line_numbers=" | ||
+ | ; We assume here that no VIC interrupts are enabled and | ||
+ | ; VASYL is the only possible video related IRQ source | ||
LDA #$10 | LDA #$10 | ||
STA $d019 | STA $d019 |
vasyl_interrupts_and_vasyl_cpu_coordination.1602063563.txt.gz · Last modified: 2020/10/07 02:39 by silverdr