Differences

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--- vasyl_interrupts_and_vasyl_cpu_coordination [2020/10/07 13:25] – laubzega
+++ vasyl_interrupts_and_vasyl_cpu_coordination [2020/10/09 00:41] – [VASYL interrupts and VASYL/CPU coordination] laubzega
@@ Line 11: / Line 11: @@
 === Non-VIC writes ===
-**MOV** and **XFER** display list instructions do an excellent job of fast, precise writes to VIC-II registers. However, there are locations in C64 memory space that influence video output, and yet are beyond VASYL's reach - a canonical example here is VIC bank switching in ''CI2PRA'' register at $dd00, but it could also be just-in-time Colour RAM or video matrix updates.
+**MOV** and **XFER** display list instructions do an excellent job of fast, precise writes to VIC-II registers. However, there are locations in C64 memory space that influence video output, and yet are beyond VASYL's reach - a canonical example here is VIC bank switching in ''CI2PRA'' register at ''$dd00'', but it could also be just-in-time Colour RAM or video matrix updates.
@@ Line 42: / Line 42: @@
         STA $315
 </code>
-  * The interrupt needs to be enabled by setting bit 4 in the ''IRQMASK'' register at $d01a (the same register that stores bits controlling VIC's interrupts),
+  * The interrupt needs to be enabled by setting bit 4 in the ''IRQMASK'' register at ''$d01a'' (the same register that stores bits controlling VIC's interrupts),
 <code [enable_line_numbers="false"]>
@@ Line 57: / Line 57: @@
         IRQ         ; trigger another interrupt, this time at the beginning of the line
 </code>
-  * In your interrupt handler, you need to make sure that VASYL IRQ is acknowledged by setting bit 4 of ''VICIRQ'' register at $d019, or the interrupt will be retriggered as soon as the handler finishes executing.
+  * In your interrupt handler, you need to make sure that VASYL IRQ is acknowledged by setting bit 4 of ''VICIRQ'' register at ''$d019'', or the interrupt will be retriggered as soon as the handler finishes executing.
 <code [enable_line_numbers="false"]>