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| registers [2020/10/18 21:09] – laubzega | registers [2022/07/27 13:35] (current) – silverdr |
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| ^ Address:bit(s) ^ Name ^ Width [bits] ^ Description ^ | ^ Address:bit(s) ^ Name ^ Width [bits] ^ Description ^ |
| | $D031 | <BOOKMARK:CONTROL>CONTROL | 8 | Main control register. Also used to activate BeamRacer after boot or Run/Stop-Restore by writing values "B" ($42, 66 dec) followed by "R" ($52, 82 dec). | | | $D031 | <BOOKMARK:CONTROL>CONTROL | 8 | Main control register. Also used to activate BeamRacer after boot or Run/Stop-Restore by writing values "B" ($42, 66 dec) followed by "R" ($52, 82 dec). | |
| | $D031:210 | RAMBANK | 3 | Number of a memory bank (0 to 7) accessible through ports. | | | $D031:210 | RAMBANK | 3 | Number of a memory bank (0 to 7) accessible through ports. If written simultaneously with bit 3 ''DLIST_ON'' cleared (displaylist processing turned OFF), also memory bank, in which displaylists are executed is changed. | |
| | $D031:3 | <BOOKMARK:DLIST_ON>DLIST_ON | 1 | When set to "1", display list execution will start at the beginning of the next frame. \\ When set to "0", display list execution stops immediately. | | | $D031:3 | <BOOKMARK:DLIST_ON>DLIST_ON | 1 | When set to "1", display list execution will start at the beginning of the next frame. \\ When set to "0", display list execution stops immediately and memory bank for displaylist execution is set in accordance with ''RAMBANK'' bits value. | |
| | $D031:4 | <BOOKMARK:PORT_READ_ENABLE>PORT_READ_ENABLE | 1 | When "1" data can be read from both memory ports. | | | $D031:4 | <BOOKMARK:PORT_READ_ENABLE>PORT_READ_ENABLE | 1 | When "1" data can be read from both memory ports. | |
| | $D031:5 | <BOOKMARK:GRAYDOT_KILL>GRAYDOT_KILL | 1 | "1" disables HMOS VIC-II grey dots visible on CPU writes to currently active color register. \\ "0" - dots are visible as usual. | | | $D031:5 | <BOOKMARK:GRAYDOT_KILL>GRAYDOT_KILL | 1 | "1" disables HMOS VIC-II grey dots visible on CPU writes to currently active color register. \\ "0" - dots are visible as usual. | |
| | $D031:76 | <BOOKMARK:RESERVED>RESERVED | 2| RESERVED. | | | $D031:76 | <BOOKMARK:CTRL_PORT_MODE>CTRL_PORT_MODE| 2| 00 - Regular port operation \\ 01 - PORT0 copies to PORT1 \\ 10 & 11 - RESERVED | |
| | $D032 | <BOOKMARK:DLISTL>DLISTL | 8 | Lo-byte of address from which execution of Display List will start at the beginning of the next frame or after a write to DLSTROBE ($D03E). | | | $D032 | <BOOKMARK:DLISTL>DLISTL | 8 | Lo-byte of address from which execution of Display List will start at the beginning of the next frame or after a write to DLSTROBE ($D03E). | |
| | $D033 | <BOOKMARK:DLISTH>DLISTH | 8 | Hi-byte of address from which execution of Display List will start at the beginning of the next frame or after a write to DLSTROBE ($D03E). | | | $D033 | <BOOKMARK:DLISTH>DLISTH | 8 | Hi-byte of address from which execution of Display List will start at the beginning of the next frame or after a write to DLSTROBE ($D03E). | |
| | $D034 | <BOOKMARK:ADR0L>ADR0L | 8 | Lo-byte of address in VASYL memory to read from or write to| | | $D034 | <BOOKMARK:ADR0L>ADR0L | 8 | Lo-byte of address in VASYL memory to read from or write to using PORT0| |
| | $D035 | <BOOKMARK:ADR0H>ADR0H | 8 | Hi-byte of address in VASYL memory to read from or write to| | | $D035 | <BOOKMARK:ADR0H>ADR0H | 8 | Hi-byte of address in VASYL memory to read from or write to using PORT0| |
| | $D036 | <BOOKMARK:STEP0>STEP0 | 8 | Value in range [-128, 127] added to ADR0(LH) after each access to PORT0 | | | $D036 | <BOOKMARK:STEP0>STEP0 | 8 | Value in range [-128, 127] added to ADR0(LH) after each access to PORT0 | |
| | $D037 | <BOOKMARK:PORT0>PORT0 | 8 | Writing stores a byte at location ADR0(LH) in currently active bank of VASYL memory. \\ Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL1 ($D031) is set to "1"). | | | $D037 | <BOOKMARK:PORT0>PORT0 | 8 | Writing stores a byte at location ADR0(LH) in currently active bank of VASYL memory. \\ Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL1 ($D031) is set to "1"). | |
| | $D038 | <BOOKMARK:ADR1L>ADR1L | 8 | Lo-byte of address in VASYL memory to read from or write to| | | $D038 | <BOOKMARK:ADR1L>ADR1L | 8 | Lo-byte of address in VASYL memory to read from or write to using PORT1| |
| | $D039 | <BOOKMARK:ADR1H>ADR1H | 8 | Hi-byte of address in VASYL memory to read from or write to| | | $D039 | <BOOKMARK:ADR1H>ADR1H | 8 | Hi-byte of address in VASYL memory to read from or write to using PORT1| |
| | $D03A | <BOOKMARK:STEP1>STEP1 | 8 | Value in range [-128, 127] added to ADR1(LH) after each access to PORT1 | | | $D03A | <BOOKMARK:STEP1>STEP1 | 8 | Value in range [-128, 127] added to ADR1(LH) after each access to PORT1 | |
| | $D03B | <BOOKMARK:PORT1>PORT1 | 8 | Writing stores a byte at location ADR1(LH) in currently active bank of VASYL memory. \\ Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL1 ($D031) is set to "1"). | | | $D03B | <BOOKMARK:PORT1>PORT1 | 8 | Writing stores a byte at location ADR1(LH) in currently active bank of VASYL memory. \\ Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL1 ($D031) is set to "1"). | |
| | $D03E | <BOOKMARK:DLSTROBE>DLSTROBE | 8 | Writing to this register will start execution of Display List pointed to by DLIST(LH) from the next cycle. \\ On reads returns VASYL version in bits 3-7 and VIC-II autoconfiguration data in bits 0-2: \\ 000 - NTSC (6567R8 or 8562) \\ 110 - PAL (6569 or 8565) \\ 100 - PAL-N (6572) \\ 011 - NTSC (6567R56A) | | | $D03E | <BOOKMARK:DLSTROBE>DLSTROBE | 8 | Writing to this register will start execution of Display List pointed to by DLIST(LH) from the next cycle. \\ On reads returns VASYL version in bits 3-7 and VIC-II autoconfiguration data in bits 0-2: \\ 000 - NTSC (6567R8 or 8562) \\ 110 - PAL (6569 or 8565) \\ 100 - PAL-N (6572) \\ 011 - NTSC (6567R56A) | |
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| Write-only registers, accessible only to VASYL (have to be written to by a Display List). | Write-only registers, accessible only to VASYL (can only be manipulated from within a running Display List). |
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| | $D041 | <BOOKMARK:DLIST2L>DLIST2L | 8 | Lo-byte of address from which execution of Display List will start after a write to DL2STROBE. | | | $D041 | <BOOKMARK:DLIST2L>DLIST2L | 8 | Lo-byte of address from which execution of Display List will start after a write to DL2STROBE. | |
| | $D042 | <BOOKMARK:DLIST2H>DLIST2H | 8 | Hi-byte of address from which execution of Display List will start after a write to DL2STROBE. | | | $D042 | <BOOKMARK:DLIST2H>DLIST2H | 8 | Hi-byte of address from which execution of Display List will start after a write to DL2STROBE. | |
| | $D043 | <BOOKMARK:DL2STROBE>DL2STROBE | 8 | Writing to this register will start execution of Display List pointed to by DLIST2(LH) from the next cycle. If MSB is set, also the RAM bank used by the Display List will change based on bits 0-2. | | | $D043 | <BOOKMARK:DL2STROBE>DL2STROBE | 8 | Writing to this register will start execution of Display List pointed to by DLIST2(LH) from the next cycle. If bit 3 is set, also the RAM bank used by the Display List will change based on bits 0-2. Please note that this does not change the display list starting point. After reaching the end, execution will be restarted from address pointed to by DLISTL/DLISTH register pair //in currently selected memory bank!// | |
| | $D044 | <BOOKMARK:S_BASEL>S_BASEL | 8 | Lo-byte of address of memory location to fetch bitmap data from. Writes to this register by default do not update internal 16-bit bitmap sequencer register. | | | $D044 | <BOOKMARK:S_BASEL>S_BASEL | 8 | Lo-byte of address of memory location to fetch bitmap data from. Writes to this register by default do not update internal 16-bit bitmap sequencer register. | |
| | $D045 | <BOOKMARK:S_BASEH>S_BASEH | 8 | Hi-byte of address of memory location to fetch bitmap data from. Writes to SBASEH update internal 16-bit bitmap sequencer register with both SBASEL and SBASEH simultaneously.| | | $D045 | <BOOKMARK:S_BASEH>S_BASEH | 8 | Hi-byte of address of memory location to fetch bitmap data from. Writes to SBASEH update internal 16-bit bitmap sequencer register with both SBASEL and SBASEH simultaneously.| |
