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VASYL registers
Read/write registers accessible to both 6510 and VASYL itself.
| Address:bit(s) | Name | Width [bits] | Description |
| $D031 | CTRL1 | 8 | Main control register. Also used to activate BeamRacer after boot or Run/Stop-Restore by writing values “B” ($42, 66 dec) followed by “R” ($52, 82 dec). |
| $D031:210 | RAMBANK | 3 | Number of a memory bank (0 to 7) accessible through ports. |
| $D031:3 | DLIST_ON | 1 | When set to “1”, display list execution will start at the beginning of the next frame.
When set to “0”, display list execution stops immediately. |
| $D031:4 | PORT_READ_ENABLE | 1 | When “1” data can be read from both memory ports. |
| $D031:5 | GRAYDOT_DISABLE | 1 | “1” disables HMOS VIC-II gray dots visible on CPU writes to currently active color register.
“0” - dots are visible as usual |
| $D031:76 | RESERVED | 1 | RESERVED - Always “0” on reads. |
| $D032 | DLISTL | 8 | Lo-byte of address from which execution of Display List will start at the beginning of the next frame or after a write to DLSTROBE ($D033). |
| $D033 | DLISTH | 8 | Hi-byte of address from which execution of Display List will start at the beginning of the next frame or after a write to DLSTROBE ($D033). |
| $D034 | ADR0L | 8 | Lo-byte of address in VASYL memory to read from or write to |
| $D035 | ADR0H | 8 | Hi-byte of address in VASYL memory to read from or write to |
| $D036 | STEP0 | 8 | Value in range [-128, 127] added to ADR0(LH) after each access to PORT0 |
| $D037 | PORT0 | 8 | Writing stores a byte at location ADR0(LH) in currently active bank of VASYL memory.
Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL1 ($D030) is set to “1”). |
| $D038 | ADR1L | 8 | Lo-byte of address in VASYL memory to read from or write to |
| $D039 | ADR1H | 8 | Hi-byte of address in VASYL memory to read from or write to |
| $D03A | STEP1 | 8 | Value in range [-128, 127] added to ADR1(LH) after each access to PORT1 |
| $D03B | PORT1 | 8 | Writing stores a byte at location ADR1(LH) in currently active bank of VASYL memory.
Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL1 ($D030) is set to “1”). |
| $D03C | REP0 | 8 | Repeats latest write to PORT0 given number of times. “0” repeats 256 times. |
| $D03D | REP1 | 8 | Repeats latest write to PORT1 given number of times. “0” repeats 256 times. |
| $D03E | DLSTROBE | 8 | Writing to this register will start execution of Display List pointed to by DLIST(LH) from the next cycle.
On reads returns VASYL version in bits 3-7 and VIC-II autoconfiguration data in bits 0-2:
000 - NTSC (6567R8 or 8562)
110 - PAL (6569 or 8565)
100 - PAL-N (6572)
011 - NTSC (6567R56A) |
Write-only registers, accessible only to VASYL (have to be written to by a Display List).
| Address:bit(s) | Name | Width [bits] | Description |
| $D040 | CTRL2 | 8 | Secondary control register |
| $D040:210 | BS_RAMBANK | 3 | Number of memory bank (0 to 7) which bitmap sequencer fetches data from. |
| $D040:3 | BS_ACTIVE | 1 | Value of “1” activates the bitmap sequencer. |
| $D040:4 | BS_UPDATE_EOL | 1 | Update bitmap sequencer pointer at the end of each line. |
| $D040:5 | BS_UPDATE_ALWAYS | 1 | Update bitmap sequencer pointer continuously (after each cycle). |
| $D040:76 | BS_MIRROR | 2 | “00” - bytes are shifted out by the sequencer as is (76543210).
“01” - bytes are shifted out in reverse bit order, e.g. LSB is the leftmost, MSB is the rightmost (01234567)
“10” - bytes are shifted out as reversed bit pairs (10325476). “11” - reserved, do not use. |
| $D041 | DLIST2L | 8 | Lo-byte of address from which execution of Display List will start after a write to DL2STROBE. |
| $D042 | DLIST2H | 8 | Hi-byte of address from which execution of Display List will start after a write to DL2STROBE. |
| $D043 | DL2STROBE | 8 | Writing to this register will start execution of Display List pointed to by DLIST2(LH) from the next cycle. If LSB is set, also the RAM bank used by the Display List will change based on bits 0-2. |
| $D044 | S_BASEL | 8 | Lo-byte of address of memory location to fetch bitmap data from. Writes to this register by default do not update internal 16-bit bitmap sequencer register. |
| $D045 | S_BASEH | 8 | Hi-byte of address of memory location to fetch bitmap data from. Writes to SBASEH update internal 16-bit bitmap sequencer register with both SBASEL and SBASEH simultaneously. |
| $D046 | S_CYC_START | 8 | Number of the first rasterline cycle to perform bitmap sequencer operation. |
| $D047 | S_CYC_STOP | 8 | Number of the first rasterline cycle to cease bitmap sequencer operation. |
| $D048 | S_STEP_L | 8 | Lo-byte of a value added to bitmap sequencer's internal memory pointer after every fetch. |
| $D049 | S_STEP_H | 8 | Hi-byte of a value added to bitmap sequencer's internal memory pointer after every fetch. |
| $D04A | S_PADDING_L | 8 | Lo-byte of a value added to bitmap sequencer's internal memory pointer at the end of every line. |
| $D04B | S_PADDING_H | 8 | Hi-byte of a value added to bitmap sequencer's internal memory pointer at the end of every line. |
