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registers [2021/06/05 10:30] – silverdr | registers [2021/09/08 09:19] – silverdr |
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| $D031:4 | <BOOKMARK:PORT_READ_ENABLE>PORT_READ_ENABLE | 1 | When "1" data can be read from both memory ports. | | | $D031:4 | <BOOKMARK:PORT_READ_ENABLE>PORT_READ_ENABLE | 1 | When "1" data can be read from both memory ports. | |
| $D031:5 | <BOOKMARK:GRAYDOT_KILL>GRAYDOT_KILL | 1 | "1" disables HMOS VIC-II grey dots visible on CPU writes to currently active color register. \\ "0" - dots are visible as usual. | | | $D031:5 | <BOOKMARK:GRAYDOT_KILL>GRAYDOT_KILL | 1 | "1" disables HMOS VIC-II grey dots visible on CPU writes to currently active color register. \\ "0" - dots are visible as usual. | |
| $D031:76 | <BOOKMARK:RESERVED>RESERVED | 2| RESERVED. | | | $D031:76 | <BOOKMARK:CTRL_PORT_MODE>CTRL_PORT_MODE| 2| 00 - Regular port operation \\ 01 - PORT0 copies to PORT1 \\ 10 & 11 - RESERVED | |
| $D032 | <BOOKMARK:DLISTL>DLISTL | 8 | Lo-byte of address from which execution of Display List will start at the beginning of the next frame or after a write to DLSTROBE ($D03E). | | | $D032 | <BOOKMARK:DLISTL>DLISTL | 8 | Lo-byte of address from which execution of Display List will start at the beginning of the next frame or after a write to DLSTROBE ($D03E). | |
| $D033 | <BOOKMARK:DLISTH>DLISTH | 8 | Hi-byte of address from which execution of Display List will start at the beginning of the next frame or after a write to DLSTROBE ($D03E). | | | $D033 | <BOOKMARK:DLISTH>DLISTH | 8 | Hi-byte of address from which execution of Display List will start at the beginning of the next frame or after a write to DLSTROBE ($D03E). | |
| $D034 | <BOOKMARK:ADR0L>ADR0L | 8 | Lo-byte of address in VASYL memory to read from or write to| | | $D034 | <BOOKMARK:ADR0L>ADR0L | 8 | Lo-byte of address in VASYL memory to read from or write to using PORT0| |
| $D035 | <BOOKMARK:ADR0H>ADR0H | 8 | Hi-byte of address in VASYL memory to read from or write to| | | $D035 | <BOOKMARK:ADR0H>ADR0H | 8 | Hi-byte of address in VASYL memory to read from or write to using PORT0| |
| $D036 | <BOOKMARK:STEP0>STEP0 | 8 | Value in range [-128, 127] added to ADR0(LH) after each access to PORT0 | | | $D036 | <BOOKMARK:STEP0>STEP0 | 8 | Value in range [-128, 127] added to ADR0(LH) after each access to PORT0 | |
| $D037 | <BOOKMARK:PORT0>PORT0 | 8 | Writing stores a byte at location ADR0(LH) in currently active bank of VASYL memory. \\ Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL1 ($D031) is set to "1"). | | | $D037 | <BOOKMARK:PORT0>PORT0 | 8 | Writing stores a byte at location ADR0(LH) in currently active bank of VASYL memory. \\ Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL1 ($D031) is set to "1"). | |
| $D038 | <BOOKMARK:ADR1L>ADR1L | 8 | Lo-byte of address in VASYL memory to read from or write to| | | $D038 | <BOOKMARK:ADR1L>ADR1L | 8 | Lo-byte of address in VASYL memory to read from or write to using PORT1| |
| $D039 | <BOOKMARK:ADR1H>ADR1H | 8 | Hi-byte of address in VASYL memory to read from or write to| | | $D039 | <BOOKMARK:ADR1H>ADR1H | 8 | Hi-byte of address in VASYL memory to read from or write to using PORT1| |
| $D03A | <BOOKMARK:STEP1>STEP1 | 8 | Value in range [-128, 127] added to ADR1(LH) after each access to PORT1 | | | $D03A | <BOOKMARK:STEP1>STEP1 | 8 | Value in range [-128, 127] added to ADR1(LH) after each access to PORT1 | |
| $D03B | <BOOKMARK:PORT1>PORT1 | 8 | Writing stores a byte at location ADR1(LH) in currently active bank of VASYL memory. \\ Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL1 ($D031) is set to "1"). | | | $D03B | <BOOKMARK:PORT1>PORT1 | 8 | Writing stores a byte at location ADR1(LH) in currently active bank of VASYL memory. \\ Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL1 ($D031) is set to "1"). | |