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PlayGround

Address	Name	Width [bits]	Description
$D030	CTRL	8	Main control register
$D030:0	DLIST_ON	1	When set to “1”, display list execution will start at the beginning of the next frame. When set to “0”, display list execution stops immediately.
$D030:1	PORT_READ_ENABLE	1	When “1” data can be read from both memory ports.
$D030:345	RAMBANK	3	Number of bank (0 to 7) accessible through memory ports.
$D30:6	RESERVED	1	RESERVED - Always “0” on reads.
$D030:7	GRAYDOT_DISABLE	1	“1” disables HMOS VIC-II gray dots visible on CPU writes “0” - dots are visible as usual
$D031	DLISTL	8	Lo-byte of address from which execution of Display List will start.
$D032	DLISTH	8	Hi-byte of address from which execution of Display List will start.
$D033	DLSTROBE	8	Writing to this register will start execution of Display List pointed to by DLIST(LH) from the next cycle. If MSB is set, bits 0-2 are copied to bits 3-5 of CTRL2 ($D040) On reads returns VASYL version in bits 3-7 and VIC-II autoconfiguration data in bits 0-2: 000 - NTSC 110 - PAL 100 - PAL-M 011 - NTSC 6567R56A
$D034	ADR0L	8	Lo-byte of address in VASYL memory to read from or write to
$D035	ADR0H	8	Hi-byte of address in VASYL memory to read from or write to
$D036	STEP0	8	Value in range [-128, 127] added to ADR0(LH) after each access to PORT0
$D037	PORT0	8	Writing stores a byte at location ADR0(LH) in currently active bank of VASYL memory. Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL ($D030) is set to “1”
$D038	ADR1L	8	Lo-byte of address in VASYL memory to read from or write to
$D039	ADR1H	8	Hi-byte of address in VASYL memory to read from or write to
$D03A	STEP1	8	Value in range [-128, 127] added to ADR1(LH) after each access to PORT1
$D03B	PORT1	8	Writing stores a byte at location ADR1(LH) in currently active bank of VASYL memory. Reading returns a byte from that location (provided PORT_READ_ENABLE bit in CTRL ($D030) is set to “1”