making_full_use_of_memory_ports
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making_full_use_of_memory_ports [2020/10/13 20:02] – [Accessing ports from a display list] laubzega | making_full_use_of_memory_ports [2020/10/18 21:56] (current) – [Inside a port] laubzega | ||
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The ports are intended to be efficient and flexible means of accessing VASYL' | The ports are intended to be efficient and flexible means of accessing VASYL' | ||
- | Each of the two ports has its own DMA channel to the local memory, and is able to make one access - either read or write - per system clock cycle. This gives a theoretical transfer rate of ~1 MB/s per port. The 6502 is too slow to saturate even one such channel, because in the best case it can write to IO region once every four cycles (e.g. using a sequence of **STA** instructions). However, since display lists are also able to write to port registers, they can use ports to manipulate local memory at great speed. And since display lists are themselves located in that memory, it opens the possibility for display lists to manipulate both themselves and the data they use. | + | Each of the two ports has its own DMA channel to the local memory, and is able to make one access - either read or write - per system clock cycle. This gives a theoretical transfer rate of ~1 MB/s per port. The 6510 is too slow to saturate even one such channel, because in the best case it can write to IO region once every four cycles (e.g. using a sequence of **STA** instructions). However, since display lists are also able to write to port registers, they can use ports to manipulate local memory at great speed. And since display lists are themselves located in that memory, it opens the possibility for display lists to manipulate both themselves and the data they use. |
Before we get to that, let's have a closer look at registers '' | Before we get to that, let's have a closer look at registers '' |
making_full_use_of_memory_ports.txt · Last modified: 2020/10/18 21:56 by laubzega