Differences

This shows you the differences between two versions of the page.

--- isa [2022/07/14 15:05] – [MOV] silverdr
+++ isa [2022/07/26 12:53] (current) – [IRQ] silverdr
@@ Line 48: / Line 48: @@
 ^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^
 | **VIRQ ** | 1 | 0 | 1 | 0 | 0 |0 | 1 | 0 |  |  |  |   |  |   |   |   |  None  |
-|Raise 6510 IRQ. \\ \\ If bit 4 of VIC-II IRQMASK register ($D01A) is set to “1”, this instruction will cause VASYL to pull down the 6510 IRQ line and set bit 4 and 7 in VICIRQ register ($D019). This will in turn cause the 6510 to start executing interrupt request from the next available (i.e. AEC line is not pulled low) cycle, assuming interrupts have not been disabled by SEI. The interrupt needs to be acknowledged by setting bit 4 in VICIRQ to "1" in the way similar to how regular VIC-II IRQs are serviced.||||||||||||||||||
+|Raise 6510 IRQ. \\ \\ If bit 4 of VIC-II IRQMASK register ($D01A) is set to “1”, this instruction will cause VASYL to pull down the 6510 IRQ line and set bit 4 and 7 in VICIRQ register ($D019). This will in turn cause the 6510 to start servicing interrupt request from the next available (i.e. when AEC line is not pulled low) cycle, unless IRQs have been disabled by SEI. The interrupt needs to be acknowledged by setting bit 4 in VICIRQ to "1", similar to how regular VIC-II IRQs are serviced.||||||||||||||||||
 ==== MASKH====