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isa [2020/10/02 17:39] – [XFER] laubzegaisa [2022/07/26 12:53] (current) – [IRQ] silverdr
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 ^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^ ^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^
 | **VIRQ ** | 1 | 0 | 1 | 0 | 0 |0 | 1 | 0 |  |  |  |   |  |   |   |   |  None  | | **VIRQ ** | 1 | 0 | 1 | 0 | 0 |0 | 1 | 0 |  |  |  |   |  |   |   |   |  None  |
-|Raise 6510 IRQ. \\ \\ If bit 4 of VIC-II IRQMASK register ($D01A) is set to “1”, this instruction will cause VASYL to pull down the 6510 IRQ line and set bit 4 and 7 in VICIRQ register ($D019). This will in turn cause the 6510 to start executing interrupt request from the next available (i.e. AEC line is not pulled low) cycle, assuming interrupts have not been disabled by SEI. The interrupt needs to be acknowledged by setting bit 4 in VICIRQ to "1" in the same way regular VIC-II IRQs are serviced.||||||||||||||||||+|Raise 6510 IRQ. \\ \\ If bit 4 of VIC-II IRQMASK register ($D01A) is set to “1”, this instruction will cause VASYL to pull down the 6510 IRQ line and set bit 4 and 7 in VICIRQ register ($D019). This will in turn cause the 6510 to start servicing interrupt request from the next available (i.e. when AEC line is not pulled low) cycle, unless IRQs have been disabled by SEI. The interrupt needs to be acknowledged by setting bit 4 in VICIRQ to "1", similar to how regular VIC-II IRQs are serviced.||||||||||||||||||
  
 ==== MASKH==== ==== MASKH====
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 ^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^ ^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^
 | **VMOV** | 1 | 1 | R5 | R4 | R3 | R3 | R1 | R0 | X7 | X6 | X5 | X4 | X3 | X2 | X1 | X0 |  R [0,63], X [0, 255]  | | **VMOV** | 1 | 1 | R5 | R4 | R3 | R3 | R1 | R0 | X7 | X6 | X5 | X4 | X3 | X2 | X1 | X0 |  R [0,63], X [0, 255]  |
-|Move value **X** to bus-accessible register **R**. \\ \\ Value **X** is transferred to a register indicated by **R**. **R** from 0 to $2E correspond to VIC-II registers $D000 to $D02E. Values starting with $31 correspond to VASYL registers $D031-$D03E. **MOV**s to VASYL registers happen internally in the chip and are guaranteed to complete in one cycle. **MOV** to any VIC-II register uses the local bus that gets isolated from the main system bus for the duration of the move. **MOVs** to VIC-II registers are impossible while VIC is occupied by memory fetches in high phase of PHI2 cycle (e.g. during badlines), and will be delayed until VIC ceases to pull the AEC line down.  ||||||||||||||||||+|Move value **X** to bus-accessible register **R**. \\ \\ Value **X** is transferred to a register indicated by **R**. **R** from 0 to $2E correspond to VIC-II registers $D000 to $D02E. Values starting with $31 correspond to VASYL registers $D031-$D03E. **MOV**s to VASYL registers happen internally in the chip and are guaranteed to complete in one cycle. **MOV** to any VIC-II register uses the local bus that gets isolated from the main system bus for the duration of the move. **MOVs** to VIC-II registers are not possible at the time VIC is occupied with memory fetches during high phase of PHI2 cycle (e.g. during badlines). Such **MOVs** will be executed after VIC finishes accessing memory and releases the AEC line. ||||||||||||||||||
  
 ==== MOVI==== ==== MOVI====
isa.1601685589.txt.gz · Last modified: 2020/10/02 17:39 by laubzega