isa
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isa [2020/09/16 22:22] – [XFER] laubzega | isa [2022/07/26 12:53] (current) – [IRQ] silverdr | ||
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^ VBASIC | ^ VBASIC | ||
| **VIRQ ** | 1 | 0 | 1 | 0 | 0 |0 | 1 | 0 | | | | | | **VIRQ ** | 1 | 0 | 1 | 0 | 0 |0 | 1 | 0 | | | | | ||
- | |Raise 6510 IRQ. \\ \\ If bit 4 of VIC-II IRQMASK register ($D01A) is set to “1”, this instruction will cause VASYL to pull down the 6510 IRQ line and set bit 4 and 7 in VICIRQ register ($D019). This will in turn cause the 6510 to start executing | + | |Raise 6510 IRQ. \\ \\ If bit 4 of VIC-II IRQMASK register ($D01A) is set to “1”, this instruction will cause VASYL to pull down the 6510 IRQ line and set bit 4 and 7 in VICIRQ register ($D019). This will in turn cause the 6510 to start servicing |
==== MASKH==== | ==== MASKH==== | ||
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^ VBASIC | ^ VBASIC | ||
| **VMOV** | 1 | 1 | R5 | R4 | R3 | R3 | R1 | R0 | X7 | X6 | X5 | X4 | X3 | X2 | X1 | X0 | R [0,63], X [0, 255] | | | **VMOV** | 1 | 1 | R5 | R4 | R3 | R3 | R1 | R0 | X7 | X6 | X5 | X4 | X3 | X2 | X1 | X0 | R [0,63], X [0, 255] | | ||
- | |Move value **X** to bus-accessible register **R**. \\ \\ Value **X** is transferred to a register indicated by **R**. **R** from 0 to $2E correspond to VIC-II registers $D000 to $D02E. Values starting with $31 correspond to VASYL registers $D031-$D03E. **MOV**s to VASYL registers happen internally in the chip and are guaranteed to complete in one cycle. **MOV** to any VIC-II register uses the local bus that gets isolated from the main system bus for the duration of the move. **MOV** to VIC-II registers are impossible while VIC is occupied | + | |Move value **X** to bus-accessible register **R**. \\ \\ Value **X** is transferred to a register indicated by **R**. **R** from 0 to $2E correspond to VIC-II registers $D000 to $D02E. Values starting with $31 correspond to VASYL registers $D031-$D03E. **MOV**s to VASYL registers happen internally in the chip and are guaranteed to complete in one cycle. **MOV** to any VIC-II register uses the local bus that gets isolated from the main system bus for the duration of the move. **MOVs** to VIC-II registers are not possible at the time VIC is occupied |
==== MOVI==== | ==== MOVI==== | ||
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^ VBASIC | ^ VBASIC | ||
| **VXFER** | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | P | R6 | R5 | R4 | R3 | R2 | R1 | R0 | R [0,127], P [0,1] | | | **VXFER** | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | P | R6 | R5 | R4 | R3 | R2 | R1 | R0 | R [0,127], P [0,1] | | ||
- | |Transfer value from port **P** to register **R**. \\ \\ A byte is read from port **P** (i.e. from a VASYL memory location pointed to by selected port's ADR(LH) register) and written to VIC-II or VASYL register **R**. Values of **R** ranging from $0 to $2E corresponds to VIC-II registers $D000 to $D02E. Values from $31 on correspond to VASYL registers $D031 and on. Values from $40 on correspond to VASYL internal registers, inaccessible through system bus (and thus without equivalents in $D0x0 IO space). |||||||||||||||||| | + | |Transfer value from port **P** to register **R**. \\ \\ A byte is read from port **P** (i.e. from a VASYL memory location pointed to by selected port's ADR(LH) register) and written to VIC-II or VASYL register **R**. Values of **R** ranging from $0 to $2E corresponds to VIC-II registers $D000 to $D02E. Values from $31 on correspond to VASYL registers $D031 and on. Values from $40 on correspond to VASYL internal registers, inaccessible through system bus (and thus without equivalents in $D0x0 IO space). \\ \\ As with **MOV**, transfers to VIC-II registers will stall VASYL if VIC is occupied by memory fetches in high phase of PHI2 cycle. |||||||||||||||||| |
isa.1600320151.txt.gz · Last modified: 2020/09/16 22:22 by laubzega