Differences

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--- isa [2020/09/01 09:20] – [MOV] corrected starting address of VASYL registers silverdr
+++ isa [2022/07/26 12:53] (current) – [IRQ] silverdr
@@ Line 48: / Line 48: @@
 ^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^
 | **VIRQ ** | 1 | 0 | 1 | 0 | 0 |0 | 1 | 0 |  |  |  |   |  |   |   |   |  None  |
-|Raise 6510 IRQ. \\ \\ If bit 4 of VIC-II IRQMASK register ($D01A) is set to “1”, this instruction will cause VASYL to pull down the 6510 IRQ line and set bit 4 and 7 in VICIRQ register ($D019). This will in turn cause the 6510 to start executing interrupt request from the next available (i.e. AEC line is not pulled low) cycle, assuming interrupts have not been disabled by SEI. The interrupt needs to be acknowledged by setting bit 4 in VICIRQ to "1" in the same way regular VIC-II IRQs are serviced.||||||||||||||||||
+|Raise 6510 IRQ. \\ \\ If bit 4 of VIC-II IRQMASK register ($D01A) is set to “1”, this instruction will cause VASYL to pull down the 6510 IRQ line and set bit 4 and 7 in VICIRQ register ($D019). This will in turn cause the 6510 to start servicing interrupt request from the next available (i.e. when AEC line is not pulled low) cycle, unless IRQs have been disabled by SEI. The interrupt needs to be acknowledged by setting bit 4 in VICIRQ to "1", similar to how regular VIC-II IRQs are serviced.||||||||||||||||||
 ==== MASKH====
@@ Line 66: / Line 66: @@
 ^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^
 | **VMOV** | 1 | 1 | R5 | R4 | R3 | R3 | R1 | R0 | X7 | X6 | X5 | X4 | X3 | X2 | X1 | X0 |  R [0,63], X [0, 255]  |
-|Move value **X** to bus-accessible register **R**. \\ \\ Value **X** is transferred to a register indicated by **R**. **R** from 0 to $2E correspond to VIC-II registers $D000 to $D02E. Values starting with $31 correspond to VASYL registers $D030-$D03F. **MOV**s to VASYL registers happen internally in the chip and are guaranteed to complete in one cycle. **MOV** to any VIC-II register uses the local bus that gets isolated from the main system bus for the duration of the move. **MOV** to VIC-II registers are impossible while VIC is occupied by memory fetches in high phase of PHI2 cycle (e.g. during badlines), and will be delayed until VIC stops pulling AEC line down.  ||||||||||||||||||
+|Move value **X** to bus-accessible register **R**. \\ \\ Value **X** is transferred to a register indicated by **R**. **R** from 0 to $2E correspond to VIC-II registers $D000 to $D02E. Values starting with $31 correspond to VASYL registers $D031-$D03E. **MOV**s to VASYL registers happen internally in the chip and are guaranteed to complete in one cycle. **MOV** to any VIC-II register uses the local bus that gets isolated from the main system bus for the duration of the move. **MOVs** to VIC-II registers are not possible at the time VIC is occupied with memory fetches during high phase of PHI2 cycle (e.g. during badlines). Such **MOVs** will be executed after VIC finishes accessing memory and releases the AEC line. ||||||||||||||||||
 ==== MOVI====
@@ Line 73: / Line 73: @@
 | **VMOVI** | 1 | 0 | 0 | R4 | R3 | R3 | R1 | R0 | X7 | X6 | X5 | X4 | X3 | X2 | X1 | X0 |  R [0,31], X [0, 255]  |
 |Move value **X** to internal VASYL register **R** + $40. \\ \\ Value **X** is transferred to a register indicated by **R**, where **R** corresponds to VASYL registers $40-$5F. Transfers are done internally in the chip and complete in one cycle. \\ \\ Note: while **MOV** and **MOVI** are technically distinct, it makes sense for an assembler or macro to combine them into one mnemonic and to generate proper opcode based on the arguments. ||||||||||||||||||
-==== NOP====
-^ NOP ^  Byte 1  ^^^^^^^^  Byte 2  ^^^^^^^^ ^
-^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^
-| **VNOP** | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 |  |  |  |   |  |   |   |   |  None  |
-|Do nothing for one cycle. \\ \\ This is a single-byte no-operation instruction. Display List processing will continue from the next cycle. ||||||||||||||||||
 ==== SETA ====
@@ Line 96: / Line 90: @@
 ^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^
 | **VSKIP** | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 |  |  |  |   |  |   |   |   |  None  |
-|Make following **WAIT** skip an instruction if past the target. \\ \\ Modifies the behavior of the next **WAIT**  instruction to be executed. Rather than waiting for its target, WAIT will compare it with the current video beam location, and if determines that the target has been already passed, the next two bytes of the Display List are skipped.  Otherwise Display List execution proceeds normally. ||||||||||||||||||
+|Make following **WAIT** skip an instruction if it reached or passed its target location. \\ \\ Modifies the behavior of the next **WAIT**  instruction to be executed. Rather than waiting for its target, WAIT will compare it with the current video beam location, and if it determines that the target has been already reached or passed, the next two bytes of the Display List are skipped.  Otherwise, WAIT does nothing and Display List execution proceeds normally. ||||||||||||||||||
+==== VNOP====
+^ VNOP ^  Byte 1  ^^^^^^^^  Byte 2  ^^^^^^^^ ^
+^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^
+| **VNOP** | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 |  |  |  |   |  |   |   |   |  None  |
+|Do nothing for one cycle. \\ \\ This is a single-byte no-operation instruction. Display List processing will continue from the next cycle. ||||||||||||||||||
 ==== WAIT====
@@ Line 121: / Line 121: @@
 ^ VBASIC  ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^B7^ B6 ^ B5 ^B4 ^B3^ B2 ^B1 ^B0 ^  Args  ^
 | **VXFER** | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | P | R6 | R5 | R4 | R3 | R2 | R1 | R0 |  R [0,127], P [0,1]  |
-|Transfer value from port **P** to register **R**. \\ \\ A byte is read from port **P** (i.e. from a VASYL memory location pointed to by selected port's ADR(LH) register) and written to VIC-II or VASYL register **R**. Values of **R** ranging from $0 to $2E corresponds to VIC-II registers $D000 to $D02E. Values from $31 on correspond to VASYL registers $D031 and on. Values from $40 on correspond to VASYL internal registers, inaccessible through system bus (and thus without equivalents in $D0x0 IO space). ||||||||||||||||||
+|Transfer value from port **P** to register **R**. \\ \\ A byte is read from port **P** (i.e. from a VASYL memory location pointed to by selected port's ADR(LH) register) and written to VIC-II or VASYL register **R**. Values of **R** ranging from $0 to $2E corresponds to VIC-II registers $D000 to $D02E. Values from $31 on correspond to VASYL registers $D031 and on. Values from $40 on correspond to VASYL internal registers, inaccessible through system bus (and thus without equivalents in $D0x0 IO space). \\ \\ As with **MOV**, transfers to VIC-II registers will stall VASYL if VIC is occupied by memory fetches in high phase of PHI2 cycle. ||||||||||||||||||