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--- caveats [2020/10/04 00:49] – laubzega
+++ caveats [2020/10/04 21:38] (current) – laubzega
@@ Line 64: / Line 64: @@
 The **JSR** is not an issue, for the same reason three-writes-in-a-row situation was not - BeamRacer does not need to stop the CPU during stack writes.
-That leaves the final scenario - execution of one of **ASL**, **LSR**, **DEC**, **INC**, **ROL** or **ROR** instructions. Each of these instruction makes - in addition to read accesses - two successive write accesses. The first stores the original value which was lead from the target location, the second - a modified one. For instance, if there is a value ''$01'' at memory location ''$8000'', instruction ''DEC $8000'' will write values ''$01'' and then ''$00'' to address ''$8000''.
+That leaves the final scenario - execution of one of **ASL**, **LSR**, **DEC**, **INC**, **ROL** or **ROR** instructions. Each of these instruction makes - in addition to read accesses - two successive write accesses. The first stores the original value which was read from the target location, the second - a modified one. For instance, if there is a value ''$01'' at memory location ''$8000'', instruction ''DEC $8000'' will write values ''$01'' and then ''$00'' to address ''$8000''.
 This is sometimes exploited to acknowledge VIC-II raster interrupt - the appropriate bit is the least significant one in register ''$d019'', so if it is set, executing, e.g. ''DEC $d019'' will with its first write achieve the equivalent of ''LDA #1; STA $d019'' (and the second write stores a value of zero, which is irrelevant in this case).
 This "trick" is not supported by BeamRacer, because only the second write gets stored and subsequently replayed if CPU and VASYL writes happen simultaneously. In any case, it is recommended that VASYL interrupts are used instead, as they have the advantage of being triggerable at any rasterline cycle, not just at its beginning.