caveats
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As is well known, the 6510 can perform up to three write accesses in sequence, and consequently needs as much time to be stopped. That's why VIC-II asserts BA line three cycles ahead of pulling down AEC - giving the CPU enough time to stop no matter what it is doing at the moment. How can then BeamRacer function with just a single-access buffer? | As is well known, the 6510 can perform up to three write accesses in sequence, and consequently needs as much time to be stopped. That's why VIC-II asserts BA line three cycles ahead of pulling down AEC - giving the CPU enough time to stop no matter what it is doing at the moment. How can then BeamRacer function with just a single-access buffer? | ||
- | First, the only situation where three write accesses in a row happen is at the start of interrupt service sequence((Execution of instruction **BRK** is a near-equivalent of this.)), when CPU writes | + | First, the only situation where three write accesses in a row happen is at the start of interrupt service sequence((Execution of instruction **BRK** is a near-equivalent of this.)), when CPU pushes |
Two writes in a row happen: | Two writes in a row happen: | ||
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The **JSR** is not an issue, for the same reason three-writes-in-a-row situation was not - BeamRacer does not need to stop the CPU during stack writes. | The **JSR** is not an issue, for the same reason three-writes-in-a-row situation was not - BeamRacer does not need to stop the CPU during stack writes. | ||
- | That leaves the final scenario - execution of one of **ASL**, **LSR**, **DEC**, **INC**, **ROL** or **ROR** instructions. Each of these instruction makes - in addition to read accesses - two successive write accesses. The first stores the original value which was lead from the target location, the second - a modified one. For instance, if there is a value '' | + | That leaves the final scenario - execution of one of **ASL**, **LSR**, **DEC**, **INC**, **ROL** or **ROR** instructions. Each of these instruction makes - in addition to read accesses - two successive write accesses. The first stores the original value which was read from the target location, the second - a modified one. For instance, if there is a value '' |
This is sometimes exploited to acknowledge VIC-II raster interrupt - the appropriate bit is the least significant one in register '' | This is sometimes exploited to acknowledge VIC-II raster interrupt - the appropriate bit is the least significant one in register '' | ||
This " | This " |
caveats.1601796600.txt.gz · Last modified: 2020/10/04 00:30 by laubzega