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--- caveats [2020/10/04 00:30] – laubzega
+++ caveats [2020/10/04 00:49] – laubzega
@@ Line 55: / Line 55: @@
 As is well known, the 6510 can perform up to three write accesses in sequence, and consequently needs as much time to be stopped. That's why VIC-II asserts BA line three cycles ahead of pulling down AEC - giving the CPU enough time to stop no matter what it is doing at the moment. How can then BeamRacer function with just a single-access buffer?
-First, the only situation where three write accesses in a row happen is at the start of interrupt service sequence((Execution of instruction **BRK** is a near-equivalent of this.)), when CPU writes program counter and status register to the stack. This is of no concern to BeamRacer, because the stack is always in the fixed location (''$100-$1ff''), certainly outside VIC-II address space, and so the writes to it never need to be postponed.
+First, the only situation where three write accesses in a row happen is at the start of interrupt service sequence((Execution of instruction **BRK** is a near-equivalent of this.)), when CPU pushes program counter (two bytes) and status register (one byte) to the stack. This is of no concern to BeamRacer, because the stack is always in the fixed location (''$100-$1ff''), certainly outside VIC-II address space, and so the writes to it never need to be postponed.
 Two writes in a row happen: