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caveats [2020/10/04 00:27] – laubzegacaveats [2020/10/04 00:49] – laubzega
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 As is well known, the 6510 can perform up to three write accesses in sequence, and consequently needs as much time to be stopped. That's why VIC-II asserts BA line three cycles ahead of pulling down AEC - giving the CPU enough time to stop no matter what it is doing at the moment. How can then BeamRacer function with just a single-access buffer? As is well known, the 6510 can perform up to three write accesses in sequence, and consequently needs as much time to be stopped. That's why VIC-II asserts BA line three cycles ahead of pulling down AEC - giving the CPU enough time to stop no matter what it is doing at the moment. How can then BeamRacer function with just a single-access buffer?
  
-First, the only situation where three write accesses in a row happen is at the start of interrupt service sequence((Execution of instruction **BRK** is a near-equivalent of this.)), when CPU writes program counter and status register to the stack. This is of no concern to BeamRacer, because the stack is always in the fixed location (''$100-$1ff''), certainly outside VIC-II address space, and so the writes to it never need to be postponed.+First, the only situation where three write accesses in a row happen is at the start of interrupt service sequence((Execution of instruction **BRK** is a near-equivalent of this.)), when CPU pushes program counter (two bytes) and status register (one byte) to the stack. This is of no concern to BeamRacer, because the stack is always in the fixed location (''$100-$1ff''), certainly outside VIC-II address space, and so the writes to it never need to be postponed.
  
 Two writes in a row happen: Two writes in a row happen:
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 This is sometimes exploited to acknowledge VIC-II raster interrupt - the appropriate bit is the least significant one in register ''$d019'', so if it is set, executing, e.g. ''DEC $d019'' will with its first write achieve the equivalent of ''LDA #1; STA $d019'' (and the second write stores a value of zero, which is irrelevant in this case). This is sometimes exploited to acknowledge VIC-II raster interrupt - the appropriate bit is the least significant one in register ''$d019'', so if it is set, executing, e.g. ''DEC $d019'' will with its first write achieve the equivalent of ''LDA #1; STA $d019'' (and the second write stores a value of zero, which is irrelevant in this case).
  
-This "trick" is not supported by BeamRacer, because only the second write gets stored and subsequently replayed if CPU and VASYL writes happen simultaneously. In any case, it is recommended that VASYL interrupts are used, as they have the advantage of being triggerable at any rasterline cycle, not just at its beginning.+This "trick" is not supported by BeamRacer, because only the second write gets stored and subsequently replayed if CPU and VASYL writes happen simultaneously. In any case, it is recommended that VASYL interrupts are used instead, as they have the advantage of being triggerable at any rasterline cycle, not just at its beginning.
caveats.txt · Last modified: 2020/10/04 21:38 by laubzega