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--- vasyl_interrupts_and_vasyl_cpu_coordination [2020/10/09 00:41] – [VASYL interrupts and VASYL/CPU coordination] laubzega
+++ vasyl_interrupts_and_vasyl_cpu_coordination [2021/04/15 12:04] (current) – [VASYL interrupts and VASYL/CPU coordination] laubzega
@@ Line 11: / Line 11: @@
 === Non-VIC writes ===
-**MOV** and **XFER** display list instructions do an excellent job of fast, precise writes to VIC-II registers. However, there are locations in C64 memory space that influence video output, and yet are beyond VASYL's reach - a canonical example here is VIC bank switching in ''CI2PRA'' register at ''$dd00'', but it could also be just-in-time Colour RAM or video matrix updates.
+**MOV** and **XFER** display list instructions do an excellent job of fast, precise writes to VIC-II registers. However, there are locations in C64 memory space that influence video output, and yet are beyond VASYL's reach - a canonical example here is VIC bank switching in ''CI2PRA'' register at ''$dd00'', but it could also be just-in-time Color RAM or video matrix updates.