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--- introduction_to_vasyl_programming [2020/05/24 19:18] – laubzega
+++ introduction_to_vasyl_programming [2020/05/24 19:22] (current) – removed laubzega
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-==== Introduction to Programming the BeamRacer ====
-=== Overview ===
-Producing non-trivial graphical effects on Commodore 64 requires a tight cooperation between main CPU and VIC-II: as VIC-II is generating video image, the 6510 waits for the electron beam sweeping the screen to reach a specific location, and then immediately writes to one or more VIC-II registers, changing colors, graphic modes, video banks, or perhaps affecting the chip’s internal circuitry to make it behave in ways unforeseen even by its designers.
-The downside of this is quite obvious - 6510 spends at least some time doing nothing but waiting for the right moment(s) to nudge the VIC-II. This can be partially alleviated with the help of interrupts, but high precision required by many advanced effects means that the CPU is otherwise unavailable for a significant portion of the video frame.
-BeamRacer lifts this responsibility from 6510’s shoulders, offering a dedicated coprocessor called VASYL (Video Assistance and Support Logic), which can be programmed to do exactly what’s needed at exactly the right time in the video frame. Together with accompanying logic chips on the BeamRacer board, VASYL can not only completely take over communication towards VIC-II, but also do this while working outside of C64’s system bus, becoming in many ways transparent to other system components.
-While simple effects can be implemented relatively quickly and with minimal programming, full depth of the board’s capabilities can only be properly realized with careful study of this manual and the accompanying examples.
-=== What is VASYL ===
-VASYL is the core logic chip on the BeamRacer board, incarnated inside Altera MAX-II EPM1270 FPGA. Working in synchrony with VIC-II, it controls various auxiliary chips and executes software programs (so-called display lists) that define what’s going to happen at particular times during the video frame. VASYL fetches display list instructions from a local memory at a maximum rate of one per system clock cycle. Some of these instructions only affect VASYL’s internal state, some have an impact on VIC-II or 6510. With careful programming, VASYL can also be made to write its own display lists, further offloading the main CPU.
-=== Initialization ===
-In order to maintain a high level of compatibility with existing C64 software, BeamRacer remains hidden on power on, and the computer behaves as if it was not there. That is, register writes are ignored, and reads report the same values as those in a vanilla C64.
-It is necessary to perform so-called “register knocking” for the board to reveal its presence. This is achieved by writing a sequence $42, $52  (screen codes for “BR”) to register $D030. To check if the board is indeed there, register $D030 can be then read and compared with “0”.
-<code  [enable_line_numbers="false"]>
-	LDX $D030
-	INX
-	BNE BEAM_RACER_ALREADY_ACTIVE
-	LDX #$42
-	STX $D030
-	LDX #$52
-	STX $D030
-	LDX $D030
-	BEQ BEAM_RACER_FOUND_AND_ACTIVATED
-	RTS 	; sadly, no Beam Racer...
-</code>
-=== Local Memory ===
-For VASYL to execute a display list, it first needs to be placed in its local memory (LRAM). BeamRacer provides VASYL with 512KiB of LRAM, organized in 8 banks of 64KiB each. The 6510 can put data into LRAM using two one-byte wide ports. Each port is built out of five registers:
-  * ADRL
-  * ADRH
-  * PORT
-  * STEP
-  * REP
-ADRL/ADRH are respectively the LSB and MSB of a 16-bit address in a LRAM memory bank. Together they determine the location where data will be written to (or read from), while register PORT is used to transfer the actual value. A following code
-<code>
-	LDA #$06
-	STA VREG_ADR0L	; we use the first of the two ports, hence 0 in the name
-	LDA #$01
-	STA VREG_ADR0H
-	LDA #$05
-	STA VREG_PORT0
-</code>
-will store value $05 into memory location $0106 of a currently selected LRAM bank. Since using that many instructions per transferred byte would be very inefficient, register STEP can be used to automatically move the destination pointer: its content (an 8-bit signed value, i.e. [-128,127]) is added to ADRL/ADRH after every transfer. A following loop copies 256 bytes to successive locations starting at LRAM address $2000:
-<code>
-	LDA #$00
-	STA VREG_ADR0L
-	LDA #$20
-	STA VREG_ADR0H
-	LDA #$01		; advance LRAM pointer by one on every transfer
-	STA VREG_STEP0
-	LDX #0
-loop:
-	LDA data,X
-	STA VREG_PORT0
-	INX
-	BNE loop
-</code>